1. Field of the Invention
This invention relates generally to a semiconductor integrated circuit memory device that includes an array of flash EEPROM memory cells. More specifically, this invention relates to a semiconductor integrated circuit memory device that includes an array of flash EEPROM memory cells and a method for providing reliable and accurate overerase correction of overerased flash memory cells. Even more specifically, this invention relates to a semiconductor integrated circuit memory device that includes an array of flash EEPROM memory cells and a method for providing bit-by-bit APDE verify of the flash EEPROM memory cells.
2. Discussion of the Related Art
FIG. 1 shows a typical configuration for an integrated circuit including a flash EEPROM memory array 100 and circuitry enabling programming, erasing, reading, and overerase correction of the memory cells in the array 100. The flash EEPROM array 100 is composed of multiple individual cells, such as cell 102. Each cell has a drain connected to a bitline, such as bitline 104, each bitline being connected to a bitline pull-up circuit 106 and column decoder 108. The source of each cell is connected to a common terminal, V.sub.SS. The control gate of each cell is connected to a wordline, such as wordline 109, that is connected to a row decoder 110.
The row decoder 110 receives voltage signals from a power supply 112 and distributes the particular voltage signals to the wordlines as controlled by a row address received from a processor or state machine 114. Likewise, the bitline pull-up circuit 106 receives voltage signals from the power supply 112 and distributes the particular voltage signals to the bitlines as controlled by a signal from the processor 114. Voltages provided by the power supply 112 are controlled by signals received from processor 114.
The column decoder 108 provides signals from particular bitlines to sense amplifiers or comparators 116 as controlled by a column address signal received from processor 114. The sense amplifiers 116 further receive signals from reference cells of reference array 118. An example of circuitry for reference array 118, as well as operation of such circuitry is provided in U.S. Pat. No. 5,828,601, entitled "Programmed Reference," and U.S. Pat. No. 5,335,198 entitled "Flash EEPROM Array With High Endurance," both of which are incorporated herein by reference. With signals from the column decoder 108 and reference array 118, the sense amplifiers 116 provide a signal indicating a state of a bitline relative to a reference cell line to which it is connected through data latches or buffers 120 to processor 114.
To program a cell in the flash memory array 100, high gate and drain voltage pulses are provided to the cell from power supply 112 while the source of the cell is grounded. For instance, during programming multiple gate voltage pulses of typically 10 volts are each applied for approximately two to three microseconds to a cell, while the drain voltage of the cell is set typically to 5.5 volts and the source of the cell is grounded. The large gate and drain voltage pulses enable electrons flowing from the source to drain to overcome an energy barrier to become "hot electrons" that are able to cross a thin dielectric layer onto the floating gate of the cell. This programming procedure, termed "hot electron injection" results in an increase of the threshold voltage for the cell, the threshold voltage being the gate-to-source voltage required for the cell to conduct.
To erase a cell in the flash memory array 100, a procedure known as Fowler-Nordheim tunneling is utilized wherein relatively high negative gate-to-source voltage pulses are applied to the cell for a few tenths of a second each. For instance, during erase multiple voltage pulses of minus 10 volts are applied to the control gate of the cell, the drain of the cell is floated and the source of the cell is set to a voltage of less than 6 volts. The large negative gate-to-source voltage pulses enable electrons to tunnel from the floating gate of a cell thereby reducing the cell's threshold voltage.
To represent a data bit, the floating gate of a cell is programmed or erased as described above. In a programmed state, the threshold voltage of a cell is typically set at a voltage of greater than 5 volts, while the threshold voltage of a cell in an erased state is typically limited to a voltage below 3.0 volts. To read a cell, a voltage in the range of 3.0 to 6 volts, typically 5 volts, is applied to the control gate. The 5 volt read pulse is applied to the gate of an array cell as well as to a cell in the reference array 118 having a threshold voltage of 5 volts. In a programming state with an array cell in array 100 having a threshold voltage above 5 volts, current provided by the reference cell with a threshold voltage of 5 volts will be greater thereby indicating a programmed cell. In an erased state with a threshold voltage of a cell in array 100 below 3.0 volts, current provided by the array cell will be greater than the reference cell with a threshold voltage of 3 volts indicating an erased cell. To verify programming or erase, a read voltage is similarly applied to both a cell in the array and to a cell in the reference array 118. For programming, a reference cell having a threshold of 5 volts is used for a comparison, while for erase, a reference cell having a threshold voltage of 3.0 volts is used for comparison.
In a typical flash memory array, all cells are erased simultaneously. Erasing of the memory cells is typically done by repeated applications of the short erase pulses as described above which are applied to each of the cells in an array, such as the flash memory array 100. After each erase pulse, erase verify is performed cell by cell to determine if each cell in the array has a threshold voltage above a limit, such as 3.0 volts. This limit is called "V.sub.t,max" and a cell that has a threshold voltage above V.sub.t,max is "undererased." If an undererased cell is detected, an additional erase pulse is applied to the entire array. With such an erase procedure, a cell that is not undererased will also be repeatedly erased and its floating gate may eventually acquire a threshold voltage below a minimum voltage called "V.sub.t,min." A cell with a threshold voltage below V.sub.t,min is referred to as being "overerased."
An overerased condition is undesirable because the programming characteristics of an overerased cell tend to deteriorate more rapidly, which reduces the number of times the cell can be programmed. The number of times that a cell can be programmed is referred to as the endurance of the cell. Overerased cells are also undesirable because they create bitline leakage current during program or read of the cell. For instance, during program or read, only one wordline carries a positive voltage, while the remaining wordlines are typically grounded. With wordlines grounded, or at 0 volts, a cell with a threshold voltage below V.sub.t,min will conduct a small but finite bitline leakage current. With substantial bitline leakage current, power supplies providing power to a bitline during programming may become overloaded. Similarly, with bitline leakage current during read, read errors may occur.
FIG. 5 illustrates the undesirable effect of bitline leakage current during programming. FIG. 5 is a simplified electrical schematic diagram of a column 500 of flash EEPROM cells 502, 504, 506, and 508. The source of each cell in the column 500 of cells is connected to a common source supply voltage V.sub.S. A programming voltage is applied to the control gate of the cell 504, which turns it on. A current I.sub.2 flows through the cell 504 from ground through the source of the cell, the channel (not shown) of the cell and the drain of the cell into the bitline BL. Ideally, the bitline current I.sub.BL is equal to I.sub.2. However, if one or more of the unselected cells, 502, 506 or 508 as illustrated in FIG. 5, have a low threshold or are overerased leakage currents I.sub.1, I.sub.3, and I.sub.4 could flow through the transistors 502, 506, and 508, respectively. The bitline current I.sub.BL would then be equal to the sum of I.sub.2 and the leakage currents I.sub.1, I.sub.3 and I.sub.4. In a typical flash EEPROM, the drains of a large number of memory transistor cells, for example 512 transistor cells are connected to each bitline. If a substantial number of cells on the bitline are drawing leakage current, the total leakage current on the bitline could exceed the cell read current. This makes it impossible to read the state of any cell on the bitline and therefore renders the memory inoperative. If a substantial number of cells on the bitline are drawing leakage current during programming, the total leakage current could exceed the capacity of the power supply thereby causing unreliable programming.
To prevent overerase, manufacturers of integrated circuits containing flash memory cells typically provide an overerase correction mechanism. FIG. 2 is a flowchart illustrating a prior art erase and overerase correction procedure. In the procedure, erase is performed first, and then overerase correction is provided. The procedure of FIG. 2 will be described in more detail below.
First, for the erase procedure, in steps 202 and 204, the row address and column address provided by processor 114 (FIG. 1) are set to an initial address. Next, in steps 206 and 208, an erase verify pulse is provided to a cell as selected by the row and column addresses. Outputs from sense amplifiers 116 (FIG. 1) are then utilized by processor 114 (FIG. 1) to determine if the cell referenced by the row and column addresses is undererased. If the cell is undererased, an erase pulse is applied in step 209 to the entire array and the erase verify steps 206 and 208 are repeated.
If the cell referred to by the row and column addresses is determined to not be undererased in steps 206 and 208, the column address is incremented in step 210. Next, in step 212, if the last column address has not been exceeded, control returns to step 206. Otherwise, in step 214 the row address is incremented, and if the last row address has not been exceeded in step 216, control is returned to step 204. If the last row has been exceeded, the column address is reset in step 218 to begin the overerase correction procedure.
Next, in the overerase correction procedure, in steps 220 and 222, power supply 112 (FIG. 1) is controlled to provide an overerase verify pulse to the bitline of the cells referred to by the column address, while wordlines remain grounded. Outputs from sense amplifiers 116 (FIG. 1) are then provided to the processor 114 (FIG. 1) to determine if the bitline referenced by the column address is providing a leakage current. If the bitline is providing a leakage current, one or more overerased cells exist, so in step 223 power supply 112 is controlled to provide an overerase correction pulse to all of the cells connected to the bitline referred to by the column address and step 220 is then repeated.
The overerase correction pulse applied in step 223 is a relatively high voltage applied to the drain of a cell, such as 6 volts, while its gate and source are typically grounded. U.S. Pat. No. 5,359,558 entitled "Flash EEPROM Array With Improved High Endurance," incorporated herein by reference discloses further details regarding application of overerase correction pulses.
If no bitline leakage current is identified in step 222, the column address is incremented in step 224. Next, in step 226, if the last column address has not been exceeded, control is returned to step 220. Otherwise, the overerase correction procedure is complete as indicated at 228.
Because overerased cells may have been present during erase verify in step 206, undererased, or programmed cells may still be present after the erase procedure is complete. In explanation, during erase, one cell in an array may erase on the order of 100 times faster than other cells. If the cell verified in step 206 is erased very slowly, while a cell in the same column is erased rapidly by continual applications of the erase pulse of step 209, the cell in the same column that erases faster may become overerased before the cell addressed in step 206 is verified as properly erased. Since during verify in step 206, the remaining cells on the column other than the cell addressed have grounded wordlines, the overerased cell will conduct a bitline leakage current. With such bitline leakage current adding to the current conducted by the addressed cell, a sense amplifier comparing the current of the addressed cell to current of a reference cell in reference array 118 will prematurely indicate for step 206 that the addressed cell has been properly erased. Thus, after completion of erase, cells may remain undererased.
FIG. 3 is a flowchart illustrating another prior art erase and overerase correction procedure. In the procedure, overerase correction is applied after application of each erase pulse. The procedure of FIG. 3 will be described in more detail below.
First, similar to FIG. 2, in steps 302 and 304, the row address and column address provided by the processor 114 (FIG. 1) are set to an initial address. Next, in steps 306 and 308, an erase verify pulse is provided to a cell as selected by the row and column addresses. Outputs from sense amplifiers 116 (FIG. 1) are then utilized by processor 114 (FIG. 1) to determine if the cell referenced by the row and column addresses is undererased. If the cell is undererased, an erase pulse is applied to the array in step 309.
Unlike the flowchart of FIG. 2, which after step 309 returns to erase verify in step 306, the column address provided by processor 114 (FIG. 1) is reset to an initial address in step 310 to begin an overerase correction procedure.
Next, in the overerase correction procedure, in steps 312 and 314, power supply 112 (FIG. 1) is controlled to provide an overerase verify pulse to the bitline of the cells referred by the column address, while wordlines remain grounded. Outputs from sense amplifiers 116 (FIG. 1) are then provided to the processor 114 (FIG. 1) to determine if there is a cell on the bitline referenced by the column address that is overerased and providing a leakage current. If there is an overerased cell on the bitline, an overerase correction pulse is applied to all the cells connected to the bitline and steps 312 and 314 are repeated.
If no overerased cells are identified in steps 312 and 314, the column address is incremented in step 316. Next, in step 318, if the last column address has not been exceeded, control is returned to step 312. Otherwise, control is returned from step 318 to 304 to return to the erase procedure.
Once the cell referred to by the row address and column address is determined to be not undererased in step 306, the column address is incremented in step 320. Next, in step 322, if the last column address has not been exceeded, control returns to step 306. Otherwise, in step 324 the row address is incremented, and if the last row address has not been exceeded in step 326, control is returned to step 306. If the last column and row have been exceeded, the combined erase and overerase procedure is complete as indicated at 328.
By applying the overerase correction procedure after each erase pulse as shown in FIG. 3, the extent to which cells are overerased will be reduced relative to the method described in FIG. 2 improving the endurance of cells in the array. Further because overerased cells are removed after each erase pulse, bitline leakage current will not be present during erase verify, thus preventing undererased cells from existing upon completion of the erase procedure.
However, the methods described by the flowcharts in FIGS. 2 and 3 do not allow the accurate determination if there are, in fact, overerased cells connected to the bitline being overerase verified. This can occur because all of the wordlines connected to the cells being overerase verified are grounded and there may be leakage current that prevents an accurate determination of whether there may be one or more cells that are overerased.
Therefore, what is needed is an accurate and reliable method of overerase verifying and overerase correction that ensures that all of the cells are actually not overerased.